Semiconductor memory devices for storing data can typically be classified into volatile memory devices and non-volatile memory devices according to whether the memory devices store or lose data when their power supplies are interrupted. Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices are examples of typical volatile memory devices and FLASH memory devices are examples of typical non-volatile memory devices. These typical memory devices represent a logical value “0” or “1” depending on whether the devices stores electrons or not. DRAM devices need to be refreshed periodically as they typically require a high capability of storing electrons. Therefore, extensive studies have been made to increase the surface area of a capacitor electrode. However, as the surface area of a capacitor electrode increases, the ability to provide highly integrated DRAM devices may be reduced.
Conventional FLASH memory cells include a gate pattern comprising a gate insulating layer, a floating gate, a dielectric layer and a control gate. Programming and erasing operations of the FLASH memory cell are achieved through the F-N (Fowler-Nordheim) tunneling effect through a gate insulating layer. The F-N tunneling typically occurs when an operation voltage is higher than a power supply voltage. Thus, FLASH memory devices typically require a separate voltage generation circuit for programming operations.
Highly integrated non-volatile, randomly accessible memory devices with a relatively simple structure may also be provided by a phase-changeable memory device. The phase-changeable memory device utilizes phase-changeable material. A chalcogenide material layer, for example, a compound material layer including germanium (Ge), stibium (Sb) and tellurium (Te) (e.g., GST layer) has conventionally been used as the phase-changeable material. Depending on an applied current (i.e., joules of heat), the phase-changeable material is electrically switched from an amorphous state to a crystalline state or to various resistivities while in the crystalline state.
FIG. 1A is a partial cross-sectional view of a conventional phase-changeable memory cell of a conventional phase-changeable memory device. Referring to FIG. 1A, a conventional phase-changeable memory device includes a lower conductive pattern (i.e., a lower electrode 10), a silicon oxide layer 12 thereon, a phase-changeable material pattern 16 and an upper conductive pattern (i.e., an upper electrode 18) on the phase-changeable material pattern 16. The phase-changeable material pattern 16 is electrically connected to the lower electrode 10 through a contact plug 14 (i.e. a heater plug) that extends through the silicon oxide layer 12. When a current flows between the upper and lower electrodes 10 and 18 of the conventional phase-changeable memory device, the crystalline state of the phase-changeable material of an active interface 20 changes depending on the intensity of the current passing through the active interface 20. The active interface 20 is an interface between the heater plug 14 and the phase-changeable material pattern 16.
FIG. 1B shows region 16a where crystalline state changes. As seen in FIG. 1B, along the direction of the arrows of FIG. 1B, a phase transition occurs from the top surface of the heater plug 14.
The current required to change the crystalline state of the phase-changeable material is affected by the active interface 20 of the phase-changeable material pattern 16 and the heater plug 14. Therefore, the smaller the active interface 20 is, the less operating current is required. Accordingly, studies that have been conducted on the phase-changeable memory device have focused on reducing the area of the active interface.
The thermal expansion coefficient of the silicon oxide layer 12 (α (SiO2)) is about 0.6 ppm/K and that of a GTS pattern (α (GTS)) is about 23 ppm/° K. As the phase-changeable memory device performs repeated memory operations resulting in a phase transition, thermal stress may occur due to the difference of thermal expansion coefficient between the phase-changeable material pattern and the silicon oxide layer. The crystalline state changes isotropically on the heater plug 14, so that edge of a top surface of the heater plug 14, that is, interfaces 20a and 20b between the material pattern 16 and the silicon oxide layer 12 may be weakened. Thus, stress-driven defects and micro damages of the interface 20a and 20b may occur and may result in an increase in leakage current. Ultimately, a phase transition may not take place at the active interface, thereby degrading stability and reliability of the memory device.